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K9K2G08U0A Document Title
Preliminary FLASH MEMORY
256M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.0 0.1
History
1. Initial issue 1. Technical note is changed 2. Notes of AC timing characteristics are added 3. The description of Copy-back program is changed 4. TSOP package is deleted 1. CE access time : 23ns->35ns (p.9)
Draft Date
May. 31. 2004 Oct. 25. 2004
Remark
Advance Preliminary
0.2
Feb. 14. 2005
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
1
K9K2G08U0A 256M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number K9K2G08U0A-V,F Vcc Range 2.7 ~ 3.6V Organization X8
Preliminary FLASH MEMORY
PKG Type WSOP1
FEATURES
* Voltage Supply - 2.7 V ~3.6 V * Organization - Memory Cell Array - (256M + 8,192K)bit x 8bit - Data Register - (2K + 64)bit x8bit - Cache Register - (2K + 64)bit x8bit * Automatic Program and Erase - Page Program - (2K + 64)Byte - Block Erase - (128K + 4K)Byte * Page Read Operation - Page Size - 2K-Byte - Random Read : 25s(Max.) - Serial Access : 30ns(Min.) * Fast Write Cycle Time - Program time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years * Command Register Operation * Cache Program Operation for High Performance Program * Intelligent Copy-Back Operation * Unique ID for Copyright Protection * Package : - K9K2G08U0A-VIB0 48 - Pin WSOP I (12X17X0.7mm) - K9K2G08U0A-FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
GENERAL DESCRIPTION
Offered in 256Mx8bit the K9K2G08U0A is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 200s on the 2112byte page and an erase operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K2G08U0As extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K2G08U0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
2
K9K2G08U0A
PIN CONFIGURATION (WSOP1)
K9K2G08U0A-VIB0,FIB0
N.C N.C DNU N.C N.C N.C R/B RE CE DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C DNU N.C I/O7 I/O6 I/O5 I/O4 N.C DNU N.C Vcc Vss N.C DNU N.C I/O3 I/O2 I/O1 I/O0 N.C DNU N.C N.C
Preliminary FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I) 48 - WSOP1 - 1217F
Unit :mm
0.70 MAX 15.400.10 0.580.04
#1
+0.07 -0.03
#48
+0.07 -0.03
0.16
12.40MAX
12.000.10
0.50TYP (0.500.06)
0.20
#24
#25 (0.01Min)
0.10 +0.075 -0.035
0~ 8
0.45~0.75 17.000.20
3
K9K2G08U0A
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 Pin Function
Preliminary FLASH MEMORY
DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE control during read operation, refer to 'Page read' section of Device operation . READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected.
CLE
ALE
CE
RE
WE
WP
R/B
Vcc Vss N.C
NOTE: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
4
K9K2G08U0A
Figure 1-1. Functional Block Diagram
VCC VSS A12 - A28 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 2048M + 64M Bit NAND Flash ARRAY
Preliminary FLASH MEMORY
A0 - A11
(2048 + 64)Byte x 131072 Data Register & S/A Cache Register
Command Command Register
Y-Gating
I/O Buffers & Latches
VCC VSS Output Driver I/0 0
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
I/0 7 CLE ALE WP
Figure 2-1. Array Organization
1 Block = 64 Pages (128K + 4k) Byte
128K Pages (=2,048 Blocks) 8 bit 2K Bytes 64 Bytes
1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 2048 Blocks = 2112 Mbits
Page Register
2K Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle A0 A8 A12 A20 A28 I/O 1 A1 A9 A13 A21 *L I/O 2 A2 A10 A14 A22 *L 64 Bytes I/O 3 A3 A11 A15 A23 *L
I/O 0 ~ I/O 7
I/O 4 A4 *L A16 A24 *L
I/O 5 A5 *L A17 A25 *L
I/O 6 A6 *L A18 A26 *L
I/O 7 A7 *L A19 A27 *L Column Address Column Address Row Address Row Address
Row Address
NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than reguired.
5
K9K2G08U0A
Product Introduction
Preliminary FLASH MEMORY
The K9K2G08U0A is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8 columns. Spare 64 columns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially connected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structures. A NAND structure consists of 32 cells. Total 135168 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K2G08U0A. The K9K2G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 256M byte physical space requires 29 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K2G08U0A. The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache program when there are lots of pages of data to be programmed. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function Read Read for Copy Back Read ID Reset Page Program Cache Program*2 Copy-Back Program Block Erase Random Data Input*1 Random Data Output*1 Read Status 1st. Cycle 00h 00h 90h FFh 80h 80h 85h 60h 85h 05h 70h 2nd. Cycle 30h 35h 10h 15h 10h D0h E0h O O Acceptable Command during Busy
NOTE : 1. Random Data Input/Output can be executed in a page. Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
6
K9K2G08U0A
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Short Circuit Current K9K2G08U0A-VCB0 K9K2G08U0A-VIB0 K9K2G08U0A-VCB0 K9K2G08U0A-VIB0 Symbol VIN/OUT VCC TBIAS TSTG Ios
Preliminary FLASH MEMORY
Rating -0.6 to + 4.6 -0.6 to + 4.6 -10 to +125 -40 to +125 -65 to +150 5 Unit V C C mA
NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, :TA=0 to 70C, K9K2G08U0A-VIB0:TA=-40 to 85C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7 0 Typ. 3.3 0 Max 3.6 0 Unit V V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Operating Current Page Read with Serial Access Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL(R/B) IOH=-400A IOL=2.1mA VOL=0.4V CE=VCC-0.2, WP=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) Test Conditions tRC=30ns, CE=VIL IOUT=0mA CE=VIH, WP=0V/VCC Min 0.8xVcc -0.3 2.4 8 Typ 10 10 10 20 10 Max 30 30 30 1 100 10 10 Vcc+0.3 0.2xVcc 0.4 mA V A mA Unit
7
K9K2G08U0A
VALID BLOCK
Parameter Valid Block Number Symbol NVB Min 2008 Typ. -
Preliminary FLASH MEMORY
Max 2048 Unit Blocks
NOTE : 1. The K9K2G08U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction up to 1K Program/ Earase cycles..
AC TEST CONDITION
(K9K2G08U0A-VCB0 :TA=0 to 70C, K9K2G08U0A-VIB0:TA=-40 to 85C K9K2G08U0A : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (Vcc:3.3V +/-10%) K9K2G08U0A 0V to Vcc 5ns Vcc/2 1 TTL GATE and CL=50pF
CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 20 20 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L X X X X X ALE L H L H L L X X X X(1) X CE L L L L L L X X X X H H X X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VCC
(2)
Mode Read Mode Write Mode Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by Command Input Address Input(5clock) Command Input Address Input(5clock)
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter Program Time Dummy Busy Time for Cache Program Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG*1 tCBSY
*2
Min -
Typ 200 3 2
Max 700 700 4 4 3
Unit s s cycles cycles ms
Nop tBERS
NOTE : 1.Typical program time is defined as the time within which more than 50% of whole pages are programmed at Vcc of 3.3V and 25'C 2. Max. time of tCBSY depends on timing between internal program completion and data in
8
K9K2G08U0A
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time ALE to Data Loading Time Symbol tCLS*1 tCLH tCS
*1
Preliminary FLASH MEMORY
Min
K9K2G08U0A* K9K2G08U0A K9K2G08U0A*
Max
K9K2G08U0A
Unit ns ns ns ns ns ns ns ns ns ns ns ns
25 10 35 10 25 25 10 20 10 45 15 100*2
15 5 20 5 15 15 5 15 5 30 10 100*2
-
-
tCH tWP tALS*1 tALH tDS*1 tDH tWC tWH tADL*2
NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low. 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 3. For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08U0A*.
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE or CE High to Output hold RE High Hold Time Output Hi-Z to RE Low RE High to WE Low WE High to RE Low Device Resetting Time (Read/Program/Erase) Symbol tR tAR tCLR tRR tRP tWB tRC tREA tCEA tRHZ tCHZ tOH tREH tIR tRHW tWHR tRST Min
K9K2G08U0A* K9K2G08U0A
Max
K9K2G08U0A* K9K2G08U0A
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
10 10 20 25 50 15 15 0 100 60 -
10 10 20 15 30 15 10 0 100 60 -
25 100 30 45 30 20 5/10/500*1
25 100 18 35 30 20 5/10/500*1
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08U0A*.
9
K9K2G08U0A
NAND Flash Technical Notes
Initial Invalid Block(s)
Preliminary FLASH MEMORY
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
No Create (or update) Initial Invalid Block(s) Table
*
Check "FFh ? Yes
Check "FFh" at the column address 2048 of the 1st and 2nd page in the block
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
10
K9K2G08U0A
NAND Flash Technical Notes (Continued)
Error in write or read operation
Preliminary FLASH MEMORY
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block.In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed blocks. Failure Mode Write Read Erase Failure Program Failure Single Bit Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
Program Error
*
Yes Program Completed
*
11
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
K9K2G08U0A
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
Preliminary FLASH MEMORY
Read Flow Chart
Start Write 00h Write Address Write 30h Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No No
Erase Error
*
Reclaim the Error
Verify ECC Yes Page Read Completed
No
I/O 0 = 0 ? Yes Erase Completed
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
1st (n-1)th nth (page)
{ {
Block A 1 an error occurs. Buffer memory of the controller. Block B 2
1st (n-1)th nth (page)
* Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid Block' table or other appropriate scheme.

12
K9K2G08U0A
NAND Flash Technical Notes (Continued)
Addressing for program operation
Preliminary FLASH MEMORY
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited.
Page 63
(64)
:
Page 63
(64)
:
Page 31
(32)
:
Page 31
(1)
:
Page 2 Page 1 Page 0
(3) (2) (1)
Page 2 Page 1 Page 0
(3) (32) (2)
Data register From the LSB page to MSB page DATA IN: Data (1) Data (64)
Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64)
13
K9K2G08U0A
System Interface Using CE don't-care.
Preliminary FLASH MEMORY
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
Figure 4. Program Operation with CE don't-care.
CLE
CE don't-care
CE
WE ALE I/Ox
80h Address(5Cycles)
Data Input
Data Input
10h
tCS CE
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Figure 5. Read Operation with CE don't-care.
CLE
CE don't-care
CE
RE ALE R/B tR
WE I/Ox
00h Address(5Cycle) 30h Data Output(serial access)
14
K9K2G08U0A
NOTE
Preliminary FLASH MEMORY
I/O I/Ox I/O 0 ~ I/O 7 DATA Data In/Out ~2112byte Col. Add1 A0~A7 Col. Add2 A8~A11 ADDRESS Row Add1 A12~A19 Row Add2 A20~A27 Row Add3 A28
Device K9K2G08U0A
Command Latch Cycle
CLE tCLS tCS CE tCLH tCH
WE
tWP
tALS ALE tDS I/Ox
tALH
tDH
Command
Address Latch Cycle
tCLS CLE tCS CE tWC tWC tWC
tWP WE tALS ALE tDS I/Ox tDH tWH tALH
tWP tALS tWH tALH
tWP tALS tWH tALH
tWP tALS tALH
tDS
tDH
tDS
tDH
tDS
tDH
Col. Add1
Col. Add2
Row Add1
Row Add2
15
K9K2G08U0A
Input Data Latch Cycle
tCLH
Preliminary FLASH MEMORY
CLE
tCH CE
ALE
tALS
WE tDS I/Ox
tWH tDH
tDS
tDH
tWP
tWP
tWP tDH tDS
tWC
DIN 0 DIN 1 DIN final*
NOTES : DIN final means 2112
Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tCEA
CE
RE tRHZ* I/Ox tRR R/B Dout tRC Dout tRHZ* tOH Dout
NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
16
tREA
tREH
tREA
tREA
tCHZ* tOH
K9K2G08U0A
Status Read Cycle
tCLR CLE tCLS tCS CE tCH tCEA tWHR RE tDS I/Ox 70h tDH tIR* tREA tCLH
Preliminary FLASH MEMORY
tWP WE
tCHZ* tOH
tRHZ* tOH Status Output
17
K9K2G08U0A
Read Operation
tCLR CLE
Preliminary FLASH MEMORY
CE tWC WE tWB tAR ALE tR RE tRR I/Ox
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
tRC
tRHZ
30h
tCHZ tOH
Dout N+2
Dout N Dout N+1 Dout M
Column Address
Row Address Busy
R/B
Read Operation(Intercepted by CE)
CLE
CE
WE tWB tAR ALE tR RE tRR I/Ox
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h
tRC
Dout N
Dout N+1
Column Address
Row Address Busy
R/B
18
Random Data Output In a Page
K9K2G08U0A
CLE tCLR
CE
WE
tWB
tAR
tWHR
ALE tR
tRC
tREA
RE tRR
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
19
30h Dout N Dout N+1
I/Ox
Column Address Busy Row Address
00h
05h
Col Add1
Col Add2
E0h
Dout M
Dout M+1
Column Address
R/B
Preliminary FLASH MEMORY
K9K2G08U0A
Page Program Operation
Preliminary FLASH MEMORY
CLE
CE
WE tADL ALE tWB tPROG
RE
Din Din N M 1 up to m Byte Serial Input
I/Ox
80h
tWC
tWC
tWC
Co.l Add1 Col. Add2
Row Add1
Row Add2 Row Add3
10h Program Command
70h Read Status Command
I/O0
SerialData Column Address Input Command
Row Address
R/B
m = 2112byte
I/O0=0 Successful Program I/O0=1 Error in Program
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
20
Page Program Operation with Random Data Input
K9K2G08U0A
CLE
CE tWC
tWC tWC
WE tADL tADL tWB tPROG
ALE
RE
Serial Data Column Address Input Command Row Address Serial Input Random Data Column Address Input Command
Serial Input
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
21
Col. Add2 Row Add1 Row Add2 Row Add3
I/Ox
Col. Add1 Col. Add2
80h 85h
Col. Add1
Din N
Din M
Din J
Din K
10h Program Command
70h Read Status Command
I/O0
R/B
Preliminary FLASH MEMORY
Copy-Back Program Operation With Random Data Input
K9K2G08U0A
CLE
CE
tWC tWB tWB tR tADL tPROG
WE
ALE
RE
Column Address Row Address Column Address
Row Address
I/Ox
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
00h 35h
85h
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Data 1
Data N
10h
70h
I/O0 Read Status Command
Busy
Copy-Back Data Input Command
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Busy
I/O0=0 Successful Program I/O0=1 Error in Program
22
R/B
Preliminary FLASH MEMORY
Cache Program Operation(available only within a block)
K9K2G08U0A
CLE
CE

tWC
WE
tWB tCBSY
tWB
tCPROG
ALE
RE
tADL
tADL
Serial Data Column Address Input Command Row Address Serial Input
I/Ox
80h
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Din N Din M 15h Program Command (Dummy) 80h
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Din N
Din 10h M Program Confirm Command (True)
70h
I/O
Max. 63 times repeatable
Last Page Input & Program
tCBSY : max. 700us
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Ex.) Cache Program R/B
80h Address & 15h Data Input Col Add1,2 & Row Add1,2 Data
tCBSY
23 tCBSY
80h Address & Data Input 15h 80h
R/B
tCBSY
tPROG
Preliminary FLASH MEMORY
70h 15h 80h 10h
I/Ox
Address & Data Input
Address & Data Input
K9K2G08U0A
BLOCK ERASE OPERATION
Preliminary FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS
RE I/Ox
60h
Row Add1
Row Add2 Row Add3
D0h
70h
I/O 0
Row Address
Auto Block Erase Setup Command
Erase Command
R/B
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
24
K9K2G08U0A
Read ID Operation
CLE
Preliminary FLASH MEMORY
CE
WE tAR
ALE
RE tREA I/Ox
90h Read ID Command 00h Address. 1cycle ECh Device Code* XXh 4th cyc.*
Maker Code Device Code
Device K9K2G08U0A
Device Code*(2nd Cycle) DAh
4th Cycle* 15h
ID Defintition Table 90 ID : Access command = 90H
Description 1st Byte 2nd Byte 3rd Byte 4th Byte Maker Code Device Code Don't care Page Size, Block Size, Spare Size, Organization
25
K9K2G08U0A
4th ID Data
Description Page Size (w/o redundant area ) 1KB 2KB Reserved Reserved 64KB 128KB 256KB Reserved 8 16 x8 x16 50ns/30ns/25ns Reserved Reserved 0 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4
Preliminary FLASH MEMORY
I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1
Blcok Size (w/o redundant area ) Redundant Area Size ( byte/512byte) Organization
0 1
Serial AccessMinimum
0 0 1 1
26
K9K2G08U0A
Device Operation
PAGE READ
Preliminary FLASH MEMORY
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
CLE CE WE ALE R/B RE I/Ox
00h Address(5Cycle) Col Add1,2 & Row Add1,2,3 30h Data Output(Serial Access)
tR
Data Field
Spare Field
27
K9K2G08U0A
Figure 7. Random Data Output In a Page
tR
Preliminary FLASH MEMORY
R/B RE I/Ox
00h Address 5Cycles 30h
Data Output
05h
Address 2Cycles
E0h
Data Output
Col Add1,2 & Row Add1,2,3
Data Field
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array( 1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
R/B I/Ox
80h Address & Data Input Col Add1,2 & Row Add1,2,3 Data Fail
tPROG
"0" 10h 70h I/O0 "1" Pass
28
K9K2G08U0A
Figure 9. Random Data Input In a Page
R/B I/Ox
80h Address & Data Input Col Add1,2 & Row Add1,2,3 Data Address & Data Input Col Add1,2 Data
Preliminary FLASH MEMORY
tPROG
"0" 85h 10h 70h I/O0 "1" Fail Pass
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/ O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be progammed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked.
Figure 10. Cache Program(available only within a block)
R/B
80h Address & Data Input*
tCBSY
tCBSY
tCBSY
tPROG
15h
80h
Address & Data Input
15h
80h
Address & Data Input
15h
80h
Col Add1,2 & Row Add1,2,3 Data
Col Add1,2 & Row Add1,2,3 Data
Col Add1,2 & Row Add1,2,3 Data
Address & 10h Data Input Col Add1,2 & Row Add1,2,3 Data
70h
R/B I/Ox
80h Address & Data Input
tCBSY
tCBSY
tCBSY
15h
70h
Status output
80h
Col Add1,2 & Row Add1,2,3 Data
Address & 15h Data Input Col Add1,2 & Row Add1,2,3 Data
70h
Status output
80h
Address & Data Input
15h
Col Add1,2 & Row Add1,2,3 Data
tCBSY
70h
Status output
80h
Address & 15h Data Input Col Add1,2 & Row Add1,2,3 Data
70h
Status output
output
Status
Check I/O1 for pass/fail
Check I/O5 for internal ready/busy Check I/O0,1 for pass/fail
29
K9K2G08U0A
Preliminary FLASH MEMORY
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. tPROG= Program time for the last page+ Program time for the ( last -1 )th page - (Program command cycle time + Last page data loading time)
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the CopyBack Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A27 must be the same between source and target page. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 11. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But if the soure page has an error bit by charge loss, accumulated copy-back operations could also accumulate bit errors. In this case, verifying the source page for a bit error is recommended before Copy-back program"
Figure 11. Page Copy-Back program Operation
R/B I/Ox
00h Add.(5Cycles) 35h
tR
tPROG
85h
Add.(5Cycles)
10h
70h
I/O0
Pass
Col. Add1,2 & Row Add1,2,3 Source Address
Col. Add1,2 & Row Add1,2,3 Destination Address
Fail NOTE: It's prohibited to operate Copy-Back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the Copy-Back program is permitted just between odd address pages or even address pages.
Figure 12. Page Copy-Back program Operation with Random Data Input
R/B I/Ox
00h Add.(5Cycles) 35h
tR
tPROG
85h
Add.(5Cycles)
Data
85h
Add.(2Cycles) Col Add1,2
Data
10h
70h
Col. Add1,2 & Row Add1,2,3 Source Address
Col. Add1,2 & Row Add1,2,3 Destination Address
There is no limitation for the number of repetition.
30
K9K2G08U0A
BLOCK ERASE
Preliminary FLASH MEMORY
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A18 to A28 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
R/B I/Ox
60h
tBERS
"0" Address Input(3Cycle) Row Add. : A12 ~ A28 Fail D0h 70h I/O0 "1" Pass
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
I/O No. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Pass/Fail Not use Not use Not Use Not Use Ready/Busy Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Ready/Busy Ready/Busy Write Protect Cache Prorgam Pass/Fail(N) Pass/Fail(N-1) Not use Not Use Not Use True Ready/Busy Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Ready/Busy Ready/Busy Write Protect Pass : "0" Pass : "0" Don't -cared Don't -cared Don't -cared Busy : "0" Busy : "0" Protected : "0" Ready : "1" Ready : "1" Not Protected Definition Fail : "1" Fail : "1"
NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
31
K9K2G08U0A
Read ID
Preliminary FLASH MEMORY
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 44h respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
CLE CE WE tAR1 ALE RE I/OX tWHR
90h 00h Address. 1cycle
tCLR tCEA
tREA
ECh Maker code
Device Code* Device code
XXh
4th Cyc.*
Device K9K2G08U0A
Device Code*(2nd Cycle) DAh
4th Cycle* 15h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
R/B I/OX
FFh
tRST
Table3. Device Status
After Power-up Operation Mode 00h command is latched After Reset Waiting for next command
32
K9K2G08U0A
READY/BUSY
Preliminary FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an opendrain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be determined by the following guidance.
Rp VCC
ibusy VOL : 0.4V, VOH : 2.4V Ready Vcc
R/B open drain output
VOH
CL
VOL Busy tf tr
GND Device
Figure 17. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25C , CL = 50pF
2.4 200
tr,tf [s]
300n
Ibusy
1.2 100 150
3m
Ibusy [A]
200n tr 100n
50 1.8 tf
0.8 0.6
2m 1m
1.8
1.8
1.8
1K
2K
3K Rp(ohm)
4K
Rp value guidance
Rp(min) =
VCC(Max.) - VOL(Max.) IOL + IL =
3.2V 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
33
K9K2G08U0A
Data Protection & Power up sequence
Preliminary FLASH MEMORY
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10s is required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software protection.
Figure 18. AC Waveforms for Power Transition
~ 2.5V VCC High
~ 2.5V
WP
WE
34
10s

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